New, stronger security mechanisms must also scale with system size in order to be useful in today's ecosystems. Leading security proposals for fine-grained isolation add TLB-like mechanisms that require system-wide shoot-downs, and others recommend parallel memory hierarchies for tags. CHERI capability protection enables both fine-grained memory safety and strong intra-program isolation without adding any scaling challenges to our existing consistency mechanisms. Today's large systems must devote significant resources to preserve consistency in memory, and CHERI capabilities exploit the existing memory-consistency mechanisms by placing all protection primitives into physical memory, with capabilities and their tags atomically joined as 257-bit words. As a result we have found there to be no significant barrier to adoption to the CHERI model, not only in software infrastructure including LLVM and FreeBSD, but also for large-scale hardware design.

Recent major cyber-security incidents (e.g., the NHS ransomware incident in 2017) and high-profile Distributed Denial of Service attacks (e.g., the Mirai botnet attack in 2016) have demonstrated that the current, context-agnostic (inter-)network architecture is not sufficient to provide for resilient communications at the onset of adversarial events. The model of the un-intelligent, data-forwarding network where (security) services are solely provided by isolated end-systems is deemed to always be one-step behind the most recently-exploited software vulnerabilities. In this talk, we will discuss work conducted within a recent EPSRC-funded project that tries to introduce the concept of situational awareness for future, mission-critical networked systems. In particular, we will look athow recent advances in networking technology can be exploited to provide infrastructural support for the flexible deployment of proactive services such as, e.g., always-on traffic monitoring and infrastructure protection against attacks. This work constitutes a first step towards future, intelligent (and resilient) information infrastructures.

The Mean Time Between Failures is expected to decrease as the size and complexity highperformance computing systems continues to increase. With this increase in the number of components, Fault Tolerance (FT) has been identified as one of the major challenges for exascale computing. One source of faults in a system are soft errors caused by cosmic rays, which can cause single or multi bit corruptions to the data held in memory.
Current solutions for protection against soft errors include hardware Error Correcting Codes (ECC). These have some disadvantages, including that they consume more power, require extra memory bandwidth and storage, and they also introduce more complexity to the hardware. ApplicationBased Fault Tolerance (ABFT) allows us to adapt an Error Detection and Correction technique to the application and its data structure.In this presentation we demonstrate ABFT techniques for Sparse Matrix Solvers using TeaLeaf, a heat conducting miniapp from the Mantevo Project.
This software-based approach fully protects the sparse matrix stored in the compressed sparse row format and the dense floating point vectors from soft errors. To protect the data we compare different error detection and/or correction methods such as Hamming Codes and CRC, and identify the trade-offs between them. Our solution requires no extra memory storage as the redundant data for the error detection and correction is stored in the least significant bits of the mantissa or in the unused bits from the integer vectors.
We also investigate tradeoff between the error detection/correction interval and the accuracy of the linear solve - performing the test and correction only once per `n’ timesteps can significantly reduce the performance overhead of the approach, at the cost of potentially performing more redundant work after an error has occurred but before it is detected.
In this presentation we will explain the details of these Application-Based Fault Tolerance techniques and how they combat soft errors, as well as presenting performance results on different architectures including x86, ARM, Intel Xeon Phi (Knights Landing) and GPUs.

The Anyscale Apps project involves the development of tools that will enable the creation of software capable of running on any scale of device, from IoT wireless systems to large data centres. The project is funded by EPSRC and aims to cater for a heterogeneous future of versatile infrastructure. Automatic adapation of software to different underlying hardware will enable faster development cycles and support the next generation of computing systems. Two demonstrators were identified as case studies to test our tools.
The smart building demonstrator incorporates a network of commodity low cost hardware including sensors to monitor occupancy of meeting rooms in the University of Glasgow School of Computing Science. In this case, edge computing is utilised to exploit the computational capabilities of the underlying hardware while being low cost and easy to scale based on a modular software design.The second case is a robot demonstrator. The distribution of load is performed through a pack of robots in order to identify a specific person in a busy room. The robots are required to perform compute-intensive tasks on low capability hardware and thus rely on offloading to perform the required task within acceptable time frames.
Both these demonstrators identify the limitations of the developed tools as well as their advantages and usability.